Analog · Mixed-Signal · RF IC Design Services

The analog edge of every SoC.

Every sensor, every radio, every real-world signal enters silicon through analog. MIXSOC designs that critical edge — data converters, RF front-ends, sensor readouts and power — from specification to proven silicon.

Discuss Your Chip Explore Capabilities
55+
Years Combined Leadership
35+
Tape-Outs Delivered
7
Production ASICs
22nm→600nm
Process Nodes
Capabilities

Full-stack analog, from femtoamps to millimeter waves.

Specification, architecture, circuit design, layout supervision, verification, tape-out and silicon validation — complete ownership of the analog signal chain.

Data Converters

High-speed and high-resolution ADCs & DACs — the core of every mixed-signal system.

  • 12-bit 8 GSPS interleaved pipelined ADC
  • 14-bit 500 MSPS pipelined ADC (22nm FDSOI)
  • 24-bit sigma-delta ADC · SAR · cyclic
  • 12-bit 8 GSPS current-steering DAC

RF & mm-Wave

Front-ends and frequency synthesis from S-band to automotive radar bands.

  • 77 GHz automotive radar analog (SoC)
  • Ka-band phased-array quad chip (SiGe)
  • Fractional-N & Integer-N PLLs to 4 GHz
  • 26 GHz programmable frequency divider

ROIC & Image Sensors

Readout ICs for infrared, visible and physical sensors — pixel to pad ring.

  • SWIR (InGaAs) ROICs — 4MP, Full-HD formats
  • Uncooled bolometer ROICs w/ on-chip NUC
  • Large-area visible & TDI array readout
  • MEMS gyro / accelerometer interfaces

Power Management

Clean, quiet power for sensitive analog and safety-critical systems.

  • LDOs 1–300 mA · PSRR −67 dB
  • Bandgap references & voltage monitors
  • DC-DC converters (incl. implantable-grade)
  • Power-on-reset & supervisory circuits

High-Speed Interfaces

Wireline links that move converter data off-chip reliably.

  • SerDes to 3 Gbps CML · 8b/10b DDR
  • LVDS / Sub-LVDS transceivers
  • Rad-hard 2.4 Gbps SerDes (space-grade)
  • On-chip PLL clock & data recovery

Functional Safety & Rad-Hard

Silicon that must not fail — on the road or in orbit.

  • ISO 26262 lifecycle — concept to production
  • FMEA / FMEDA · safety mechanisms
  • RHBD / RHBM CMOS · cold-sparing
  • Space-grade LVDS & SerDes heritage

Markets Served

Automotive ADAS Space & Satellite Defence & Aerospace Medical Implants Industrial Imaging Communications
Silicon Heritage

Our leadership has shipped silicon that ships in products.

Before founding MIXSOC, our team designed and validated production ICs for automotive, space, defence and medical programs.

Automotive · ISO 26262

77 GHz 4D Digital Imaging Radar-on-Chip

Analog/RF design, safety mechanisms, tape-out and silicon validation on a FuSa-certified ADAS radar SoC deployed in production vehicles.

Clocking · synthesis · LDO · bias | certified
Defence · High-Speed Conversion

8 GSPS Data Converter Suite

12-bit 8 GSPS time-interleaved pipelined ADC and quad-switching current-steering DAC for digital channelized transceiver SoCs, in 28 nm.

SINAD 52 dB target · SFDR 55 dB @ Nyquist
Imaging · Infrared

SWIR & Bolometer Readout ICs

InGaAs SWIR ROICs up to 4-megapixel formats and uncooled thermal imaging readouts with on-chip non-uniformity correction — designed for European and Indian imaging leaders.

BDI pixels 5.55 µm pitch · rad-tolerant layout
Space · ISRO Heritage

Radiation-Hardened Interface ICs

2.4 Gbps rad-hard SerDes and 8-channel cold-sparing LVDS driver/receiver sets for satellite payloads.

RHBD · fail-safe · on-chip termination
Medical · Implantable

Cochlear Implant Mixed-Signal SoC

Behind-the-ear unit integrating microphone preamp, 16-bit sigma-delta ADC and 8-channel CIS filtering in 40 nm CMOS.

Implantable-grade DC-DC · ECG/EEG conditioning
Communications · Phased Array

Ka-Band Quad Beamformer Chip

Four independent Tx/Rx chains with 7-bit phase shifters, VGAs and LNAs in 130 nm SiGe BiCMOS for phased-array systems.

17 dBm drive · vector-modulator phase control
How We Work

Specification to proven silicon. One accountable team.

A disciplined flow refined across 35+ tape-outs — with sign-off quality gates at every stage.

Spec
Architecture
Circuit Design
Layout
Verification
Tape-Out
Si Validation
Leadership

Led by engineers who still design.

Hands-on leadership with silicon heritage across DRDO, ISRO, Uhnder, Sony, Xenics and Analog Devices programs.

M Kumar
M Kumar
CEO
27 years in VLSI design. Built and led a national analog/RF IC division delivering 15+ ICs from spec to deployment.
  • Division HeadNational Analog, Mixed-Signal & RF IC design programs
  • 8 GSPS ADC/DAC · mm-wave programsKa-band phased array · cochlear SoC · SONAR AFE
  • 15+ ICs fabricated & deployedSatellite receivers · ROICs · sensor interfaces
  • M.Tech, MicroelectronicsIIT Bombay
Dinesh Kumar
Dinesh Kumar
Managing Director
19 years in Analog & RF IC design. 18+ tape-outs, 7 production ASICs. ISO 26262 functional-safety specialist.
  • Principal Design EngineerAlphacore Inc — 22 nm FDSOI ADC, PLL, PMU
  • Senior Staff EngineerUhnder / MulticoreWare — 77 GHz radar SoC
  • Group Head, Analog DesignDigicomm Semiconductor — built 14-eng. team
  • M.Tech, Electronics DesignTezpur Central University
Shashank Lingala
Shashank Lingala
Senior Manager
13+ years in analog IC design, specialized in image-sensor and physical-sensor readout — pixel to chip-top.
  • Senior ROIC Design EngineerXenics N.V., Belgium — SWIR InGaAs ROICs
  • Analog IC Design EngineerLuminasic — large-area visible & TDI ROICs
  • Consultant at Sony, Japanvia Elveego — CMOS image sensor verification
  • M.Eng.Kyushu University, Japan
Contact

Have a signal chain to build?

From a single IP block to a full mixed-signal SoC, we scope engagements around your architecture, node and schedule.

  • Email info@mixsocdesign.com
  • Phone +91 9742324488
  • Office Hyderabad, Telangana, India
  • Engage IP design · turnkey ASIC · consulting · FuSa

Join the team

We're building India's most hands-on analog design house. If you love transistors more than slides, we'd like to meet you.

careers@mixsocdesign.com